1. Field of the Invention
The present invention relates to a semiconductor device and a method of forming the same, and more particularly to a semiconductor device integrating at least a memory circuit and at least an analogue circuit which includes an improved capacitive element, and a method of forming the same.
All of patents, patent applications, patent publications, scientific articles and the like, which will hereinafter be cited or identified in the present application, will, hereby, be incorporated by references in their entirety in order to describe more fully the state of the art, to which the present invention pertains.
2. Description of the Related Art
In recent years, a large number of a semiconductor device, which comprises a logic circuit hybridized with a memory circuit, have been designed for response to various purposes and applications. For example, a DRAM-hybrid logic circuit has been provided, wherein DRAM cells integrated into a logic circuit. Capacitive elements may, in case, be needed for not only a digital circuit which constitutes the DRAM cells but also an analogue circuit which constitutes the logic circuit. The capacitive element included in the analogue circuit for the logic circuit is formed in a separate process from another process for forming the other capacitive element included in the digital circuits for the DRAM cells. It may be possible that the capacitive element for the DRAM cell utilizes a polycrystalline silicon for at least one of paired top of bottom electrodes of the cell. This capacitive element having one or more polycrystalline silicon electrodes in the DRAM cell is not suitable as the capacitive element for the analogue circuit, in the light of capacitance value dependency upon applied voltage to the capacitive element.
The capacitive element varies in capacitance value, depending upon the variation of the applied voltage. This capacitance value dependency upon applied voltage may not be influential to the DRAM cell but may be influential to the analogue circuit. An ideal capacitive element in the analogue circuit is free of any substantial capacitance value dependency upon applied voltage.
For example, an MOS capacitor includes a part of a substrate and a gate electrode of a MOS transistor. Such MOS capacitor has a substantial capacitance value dependency upon applied voltage. For this reason, such the MOS transistor is unsuitable for the analogue circuit. Also, the capacitor constituting the DRAM cell has a substantial capacitance value dependency upon applied voltage. For this reason, such DRAM cell capacitor is also unsuitable for the analogue circuit. For those reasons, the process for forming the capacitor in the analogue circuit is separated from the process for forming the capacitor in the DRAM circuit.
FIG. 1 is a fragmentary cross sectional elevation view illustrative of a conventional structure of a semiconductor device including a DRAM region and an analogue circuit region in the prior art. The semiconductor device includes a DRAM region 1000 and an analogue circuit region 2000 over a silicon substrate 201. The DRAM region 1000 includes a DRAM cell and its peripheral circuits.
Over the silicon substrate 201, p-well regions 203 and n-well region 204 are selectively formed, so that the p-well regions 203 are isolated from each other by shallow trench isolations 202. The p-well regions 203 are included in the DRAM region 1000 and the analogue circuit region 2000, respectively. The p-well regions 203 are isolated from each other by the n-well region 204.
Over the p-well regions 203 in the DRAM region 1000 and the analogue circuit region 2000, a gate insulation film 205 is formed. Gate electrodes 206 are then formed on the gate insulation film 205. Further, source and drain regions 207 are selectively formed in upper regions of the p-well regions 203 in the DRAM region 1000 and the analogue circuit region 2000, whereby first and second transistors TR11 and TR12 are formed in the DRAM region 1000 and the analogue circuit region 2000, respectively.
An inter-layer insulator 208 is then formed over the p-well regions 203 and the n-well region 204, so that the inter-layer insulator 208 overlies the first and second transistors TR11 and TR12. A planarization to a surface of the inter-layer insulator 208 is then made to form a planarized surface of the inter-layer insulator 208.
A contact hole is formed in the inter-layer insulator 208 in the DRAM region 1000. A contact plug 209 of polysilicon is formed in the contact plug. A silicon oxide film 210 is formed over the planarized surface of the inter-layer insulator 208. A surface of the silicon oxide film 210 is then planarized. Cylinder-shaped holes 216 are formed in the silicon oxide film 210, wherein the cylinder-shaped holes 216 are positioned in the DRAM region 1000 and the analogue circuit region 2000. The cylinder-shaped holes 216 are much larger in diameter than the contact hole, within which the contact plug 209 has been formed. Conductive polysilicon films 211 with surface roughness are formed on bottom and side walls of the cylinder-shaped holes 216. Silicon nitride films 212 are formed on rough surfaces of the conductive polysilicon films 211, wherein the silicon nitride films 212 act as capacitive insulation films.
Conductive polysilicon films 213 are formed on the silicon nitride films 212 and on parts of the planarized surface of the silicon oxide film 210, so that the conductive polysilicon films 213 completely fill the cylinder-shaped holes 216 and also extends over parts of the planarized surface of the silicon oxide film 210, whereby a first capacitor C11 is formed in the DRAM region 1000. In the DRAM region 1000, the conductive polysilicon film 213 acts as a top electrode of the first capacitor C11 in the DRAM region 1000. In the analogue circuit region 2000, the conductive polysilicon film 213 acts as a bottom electrode of a second capacitor C12 to be formed by further processes to be described below.
A capacitive insulation film 214 is selectively formed on a part of a top surface of the conductive polysilicon film 213 in the analogue circuit region 2000. A top electrode 215 of tungsten silicide is selectively formed on the capacitive insulation film 214, whereby the second capacitor C12 is formed in the analogue circuit region 2000.
An inter-layer insulator 217 is formed over the first and second capacitors C11 and C12. A surface of the inter-layer insulator 217 is then planarized. Contact holes are formed in the inter-layer insulator 217, so that the contact holes communicate with the top electrode 213 of the first capacitor C11, the top and bottom electrodes 215 and 213 of the second capacitor C12. Contact plugs 218 are then formed on the contact holes, so that the contact plugs 218 are connected with the top electrode 213 of the first capacitor C11, and the top and bottom electrodes 215 and 213 of the second capacitor C12. Interconnections 219 are formed on the planarized surface of the inter-layer insulator 217, wherein the interconnections 219 are connected with the contact plugs 218. The interconnections 219 are electrically connected through the contact plugs 218 to the top electrode 213 of the first capacitor C11, and the top and bottom electrodes 215 and 213 of the second capacitor C12.
In the analogue circuit region 2000, the second capacitor C12 has the bottom electrode 213 of the conductive polysilicon and the top electrode 215 of tungsten silicide. In the DRAM region 1000, the first capacitor C11 has. the top and bottom electrodes 213 and 211, both of which are made of polysilicon. The above materials for the top and bottom electrodes 215 and 213 of the second capacitor C12 are effective to reduce the capacitance dependency upon applied voltage.
As described above, the second capacitor C12 is formed in the analogue circuit region 2000 after the first capacitor C11 is formed in the DRAM region 1000. Namely, the above described respective processes for forming the first and second capacitors C11 and C12 are partly common to each other but partly dedicated to the second capacitor C12. This means that a large number of the necessary steps are needed for forming both the first and second capacitors C11 and C12. Namely, after the first capacitor C11 has been completed in the DRAM region 1000, then the capacitive insulation film 214 and the top electrode 215 are formed by the additional steps for post-forming the second capacitor C12 in the analogue circuit region 2000.
In the analogue circuit region 2000, both the top and bottom electrodes 215 and 213 of the second capacitor C12 are electrically connected through the contact plugs 218 to the overlying interconnections 219. The second transistor TR12 is electrically connected through the interconnections 219 and the contact plugs 218 to the top and bottom electrodes 215 and 213 of the second capacitor C12, which is not completely illustrated in FIG. 1. A routing length of the interconnection which connects the second capacitor C12 and the second transistor TR12 is long. This causes a remarkable parasitic capacitance which provides a certain influence to the capacitance value of he second capacitor C12.
Furthermore, the contact plug 218 to the top electrode 215 of the second capacitor C12 in the analogue circuit region 2000 is formed in the same process or at the same time as the contact plug 218 to the top electrode 213 of the first capacitor C11 DRAM region 1000. For forming the contact plug 218 to the top electrode 215, it is necessary to realize a highly accurate control in etching the inter-layer-insulator 217 for the purpose of avoiding the contact plug 218 to penetrate the top electrode 215.
In order to have reduced the above-described problems, another conventional technique has been proposed, which is disclosed in Japanese laid-open patent publication No. 11-87639, wherein the first capacitor in the DRAM region and the second capacitor in the analogue circuit region or the logic circuit region are formed in the common processes. First and second transistors are formed in the DRAM region and the analogue circuit region. An inter-layer insulator is formed over the first and second transistors. In both the DRAM region and the analogue circuit region, bottom electrodes, dielectric films and top electrodes are laminated over the inter-layer insulator for forming both the first and second capacitors in the common processes. The first and second capacitors have a metal-insulator-metal (MIM) structure, wherein the top and bottom electrodes may comprise titanium nitride.
Since the first and second capacitors are formed in the common processes, a total number of the necessary steps for forming both the first and second capacitors is reduced. Further, the metal-insulator-metal (MIM) structure contributes to reduce the capacitance dependency upon applied voltage of the second capacitor in the analogue circuit region.
In the DRAM region, both the top and bottom electrodes of the first capacitor are electrically connected through contact plugs, which are formed in the underlying inter-layer insulator, to the first transistor on the silicon substrate.
In the analogue circuit region, both the top and bottom electrodes of the second capacitor are electrically connected through contact plugs, which are formed in the overlying inter-layer insulator, to the interconnections on the top surface of the overlying inter-layer insulator.
For each of the first and second capacitors in the DRAM region and the analogue circuit region, it is necessary that the top and bottom electrodes are displaced in a horizontal direction, so that the top and bottom electrodes do never overlap in the plan view. This makes it difficult to further reduce each occupied area in plan view or each horizontal size for each of the first and second capacitors in the DRAM region and the analogue circuit region.
In the analogue circuit region, the second capacitor is electrically connected through the overlying contact to the overlying interconnection which is further connected through another contact to the underlying transistor on the substrate. This structure has a large resistance of the electrical connections between the second capacitor and the transistor.
In the above circumstances, the development of a novel semiconductor device free from the above problems is desirable.
Accordingly, it is an object of the present invention to provide a novel semiconductor device free from the above problems.
It is a further object of the present invention to provide a novel semiconductor device having a digital circuit region including a first capacitor and an analogue circuit region including a second capacitor, wherein formations of the first and second capacitors need a reduced number of fabrication processes.
It is a still further object of the present invention to provide a novel semiconductor device having a digital circuit region including a first capacitor and an analogue circuit region including a second capacitor, wherein the second capacitor in the analogue circuit region has a reduced capacitance dependency upon applied voltage.
It is yet a further object of the present invention to provide a novel semiconductor device having a digital circuit region including a first capacitor and an analogue circuit region including a second capacitor, wherein each of the first and second capacitors have reduced horizontal sizes for realizing high density.
It is further more object of the present invention to provide a novel semiconductor device having a digital circuit region including a first capacitor and an analogue circuit region including a second capacitor, wherein the second capacitor in the analogue circuit region has an electrical connection with a reduced resistance to another element in the analogue circuit region.
It is another object of the present invention to provide a novel method of fabricating a semiconductor device free from the above problems.
It is further another object of the present invention to provide a novel method of fabricating a semiconductor device having a digital circuit region including a first capacitor and an analogue circuit region including a second capacitor, wherein formations of the first and second capacitors need a reduced number of fabrication processes.
It is still another object of the present invention to provide a novel method of fabricating a semiconductor device having a digital circuit region including a first capacitor and an analogue circuit region including a second capacitor, wherein the second capacitor in the analogue circuit region has a reduced capacitance dependency upon applied voltage.
It is yet another object of the present invention to provide a novel method of fabricating a semiconductor device having a digital circuit region including a first capacitor and an analogue circuit region including a second capacitor, wherein each of the first and second capacitors have reduced horizontal sizes for realizing high density.
It is an additional object of the present invention to provide a novel method of fabricating a semiconductor device having a digital circuit region including a first capacitor and an analogue circuit region including a second capacitor, wherein the second capacitor in the analogue circuit region has an electrical connection with a reduced resistance to another element in the analogue circuit region.
A semiconductor device includes: at least a digital circuit and at least an analogue circuit. The digital circuit further includes at least a first capacitive element of metal-insulator-metal structure, which further comprises a first bottom electrode layer, a first capacitive insulation layer and a first top electrode layer. The analogue circuit further includes at least a second capacitive element of metal-insulator-metal structure, which further comprises a second bottom electrode layer, a second capacitive insulation layer and a second top electrode layer. The first and second bottom electrode layers respectively comprise separated two parts derived from a first common metal layer. The first and second capacitive insulation layers respectively comprise separated two parts derived from a common insulation layer. The first and second top electrode layers respectively comprise separated two parts derived from a second common metal layer. The second bottom electrode of the second capacitor is electrically connected with at least a first contact in a first inter-layer insulator which underlies the second bottom electrode. The second top electrode of the second capacitor is electrically connected with at least a second contact in a second inter-layer insulator which overlies the second top electrode.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.